Junctionless transistors (JLTs) provide advantages for sub 100 nanometer dimensions. In particular, JLTs have improved isolation due to low leakage current. Further, JLTs have a lower off capacitance and better linearity due to the absence of a source-drain extension and junctions. JLTs also have lower mobility degradation, which results in a lower on-state resistance.
JLTs and accumulation mode transistors (AMTs) do not have an independent control for dynamic threshold voltage (i.e., Vth) control. The threshold voltage (Vth) is controlled by the process (e.g., gate oxide thickness, Tox, substrate on insulator thickness, Tsi) and/or the material (e.g., flat-band voltage, VFB). Further, there is no dynamic control for leakage current (i.e., Ioff) and breakdown voltage (BV).
In JLTs and AMTs, on-state (i.e., on-state current, Ion) and off-state (i.e., Vth, sub-threshold slope) characteristics are inversely related to each other. In other words, the on-state and off-state characteristics vary anti-symmetrically with process parameters (e.g., Channel doping, Nch, VFB, etc.) In a typical JLT and AMT, a p type (or n type) channel is formed under the gate to electrically connect source and drain. In the typical JLT and AMT, a gate terminal modulates the conductivity of the P channel, which allows the transistor to operate.